Width of transistor gate11/18/2023 ![]() The residual SiGe is characterized by measuring (virtually) the contact area between the silicon and SiGe within the nanosheets (while ignoring the epitaxially grown Source/Drain SiGe). Using this technique, a virtual design of experiment that varies the etch time, etch lateral ratio, etch selectivity (between SiGe and Si) and channel width can be completed, to determine an optimal set of tradeoffs during the GAA channel release process. These tradeoffs between residual SiGe, silicon over etching and channel width can be better understood using semiconductor process simulation and virtual process window exploration. On the other hand, attempting to minimize the silicon loss can cause residual SiGe to remain after the channel release step, leading to suboptimal device performance. An aggressive etch process that removes all residual SiGe can lead to undesirable silicon loss. In practice, however, process engineers perform a trade-off between leaving some residual SiGe and over etching the surrounding silicon. An ideal etch process would remove all of the SiGe without removing any silicon. This process step is used to etch away the SiGe that has been deposited between the Si nanosheets. A key process during the fabrication of GAA transistors involves the channel release step. ![]() In a GAA transistor, the gate oxide surrounds the channel in all directions. Gate-all-around (GAA) architectures are an example of this type of 3D device. One method to overcome this problem is to move away from planar transistor architectures toward 3D devices. As transistor sizes shrink, short channel effects make it more difficult for transistor gates to turn a transistor ON and OFF.
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